1. Field of the Invention
The present invention relates to a power supply circuit for supplying a predetermined voltage to a load. More particularly, the present invention relates to a power supply circuit having a function of suppressing fluctuations in output voltage thereof caused by load fluctuations.
2. Description of the Prior Art
FIG. 4 is a circuit diagram of an n-channel FET driver 200 included in a conventional power supply circuit. In this n-channel FET driver 200, a positive side of a reference voltage source 2 is connected to a non-inverting input terminal (+ terminal) of a differential amplifier 1 by way of a line L3, and a feedback line L2 is connected to an inverting input terminal (− terminal) of the differential amplifier 1. A negative side of the reference voltage source 2 is grounded. Moreover, a gate of an n-channel FET 3 (hereinafter FET 3), i.e., an output current control element, is connected to an output terminal of the differential amplifier 1 by way of a line L4.
A drain of the FET 3 is connected to a first power supply E1 by way of a line L6, and a source of the FET 3 is connected to an output line L1. The feedback line L2, while being connected to the inverting input terminal (− terminal) of the differential amplifier 1, is also connected to the output line L1. One side of a capacitor 4 and one side of a load 5 are connected to this output line L1 respectively. Another side of the capacitor 4 and another side of the load 5 are connected to ground respectively.
The differential amplifier 1 converts a difference between a reference voltage Vref fed to the non-inverting terminal (+ terminal) thereof from the reference voltage source 2 and a feedback voltage Vb fed to the inverting terminal (− terminal) thereof through the feedback line L2 into a current according to a voltage-current conversion efficiency defined by a mutual conductance (or gain) Gm of the differential amplifier 1. The current thus converted is fed to the gate of the FET 3 through the line L4. This differential amplifier 1 is also connected to a second power supply E2 through a power supply line L7 and to ground through a grounding line L8.
Described hereinafter is how the n-channel FET driver 200 configured as above operates.
The differential amplifier 1 converts the difference between the reference voltage Vref fed to the non-inverting terminal (+ terminal) thereof from the reference voltage source 2 through the line L3 and the feedback voltage Vb fed to the inverting terminal (− terminal) thereof through the feedback line L2 into a current at the conversion efficiency in accordance with the mutual conductance Gm of the differential amplifier 1. The output current thus converted is fed to the gate of the FET 3 through the line L4. Accordingly, the FET 3 passes a source current thereof in accordance with the gate current thereof through the output line L1. Then, a voltage resulted from the source current is supplied to the load 5 as an output voltage Vo that also appears on the feedback line L2 as the feedback voltage Vb.
For example, assume that the load 5 changes from a heavy load to no load. Then, as shown in FIG. 5A, an output current (load current) Io becomes zero during a period T1 in which no load is applied. When the load 5 becomes a heavy load again after the period T1, the level of the output current Io becomes that under the heavy-load condition. The output voltage (load voltage) Vo changes according to changes of the output current Io as shown in FIG. 5B. In addition, a gate voltage Vg of the FET 3 changes as shown in FIG. 5C. All of these are the results of the operations described below.
When the load 5 changes from a heavy load to no load and the output current Io becomes zero, the output voltage Vo starts rising at a time point t1 and onward due to a transient phenomenon. The output voltage Vo increases by a voltage V2 at a time point t12 and returns to a predetermined voltage at a time point t8. The gate voltage Vg that is fed to the gate of the FET 3 from the differential amplifier 1 drops at the time point t1 and turns off at a time point t10 so as to curb the increase of the output voltage Vo. Thereafter, the gate voltage Vg is held at an L-level until a time point t3 during which the FET 3 remains off.
In other words, when the load 5 changes from a heavy load to no load, the output current Io becomes zero at the time point t1. However, the output voltage Vo is raised by a depth of the voltage V2 due to a transient phenomenon after the time point t1. Here, the voltage V2 is relatively high, and individual periods from the time point t1 to the time point t12 and from the time point t1 to the time point t8 are also relatively long.
Next, at the time point t3, the load 5 changes from no load to a heavy load. Then the output current Io starts flowing through the load 5. Furthermore, the output voltage Vo starts descending at the time point t3 and onward due to a transient phenomenon and drops by a voltage V2′ at the time point t13. Thereafter, the output voltage Vo starts rising so as to return to the predetermined voltage at a time point t9. The voltage V2′ is large in depth, and individual periods from the time point t3 to the time point t13 and from the time point t3 to the time point t9 are relatively long.
However, in the conventional power supply circuit configured as above, when the load 5 changes from a heavy load to no load or to a light load, the larger the capacitance of the capacitor 4 is, the longer time it takes for the output voltage Vo to return to its predetermined voltage from its raised position. Because of this reason, fluctuation values of the output voltage Vo become larger, and thereby the transient response required for quickly stabilizing the output voltage Vo is worsened.
Furthermore, when the load 5 changes from no load or a light load to a heavy load as described above, the gate voltage of the FET 3 must respond and rise from a low voltage. Therefore, the response of the FET 3 is delayed according to the gate voltage thereof, which worsens the transient response on start-up of the load 5. In the conventional power supply circuit configured in this way, the slow transient response does not cause any serious harm when the load fluctuating frequency is low. However, when the load fluctuating frequency is high, it becomes impossible to stabilize the output voltage Vo quickly, because the FET 3 is unable to respond to that high frequency.
In addition, there is another type of conventional power supply circuit in which a current in the order of a few mA is drawn into the differential amplifier also under no-load condition so as to suppress fluctuations of the output voltage caused by fluctuations in the load by reducing an impedance component or the like of an output feedback resistor. However, because the output feedback resistor is used, also in this case, the larger the capacitance of a capacitor connected in parallel to the load becomes, the longer time it takes for the output voltage to return to its predetermined voltage from its raised position when the load changes from a heavy load to no load or to a light load. Because of this reason, fluctuations of the output voltage become larger, and thereby the transient response required for quickly stabilizing the output voltage is worsened.
A semiconductor device and a supply voltage generating circuit disclosed in Japanese Patent Application Laid-Open No. H08-190437 uses a p-channel FET as an output current control element. In this configuration, an input voltage required for the p-channel FET should be set higher, which worsens its output efficiency. This disclosure also has a shortcoming in which two resistor elements are used for suppressing the amplitude of an output signal fed from a comparator circuit, thereby causing unnecessary power consumption.